The present invention relates generally to a semiconductor memory device such as a SRAM (Static Random Access Memory) and more particularly to semiconductor memory device that may be capable of reducing a propagation time difference among all memory cells in a memory cell region.
In a semiconductor memory device such as a SRAM (Static Random Access Memory), it is desirable to provide a large memory capacity, high-speed operation, reduced manufacturing costs, and the like. In order to provide these features, miniaturization of the semiconductor device components is rapidly being advanced.
Referring now to FIG. 30, a circuit schematic diagram of a conventional semiconductor memory device is set forth and given the general reference character 10. Conventional semiconductor memory device 10 is a SRAM and includes word lines (WL1 to WLn) extending in a row direction and bit lines (BL1-BLm and /BL1-/BLm) extending in a column direction. A plurality of memory cells 11 are placed at intersections of word lines WL and bit lines (BL and /BL) to form a matrix pattern. Conventional semiconductor memory device 10 includes a plurality of select circuits 12 and a plurality of reading circuits 13. Each select circuit 12 is connected to an associated word line WL. Each reading circuit 13 is connected to an associated bit line pair (BL and /BL). Bit lines (BL1-BLm and /BL1-/BLm) form bit line pairs, where BL indicates a true bit line and /BL indicates a complement bit line in a bit line pair (xe2x80x9c/xe2x80x9d indicates an inversion signal).
In semiconductor memory device 10, select circuit 12 provides a select signal on a word line WL to select a memory cell 11. Data (memory information) is read from the selected memory cell 11 by a reading circuit 13 connected to a bit line pair (BL and /BL). The distance from the memory cell 11 to a select circuit 12 and/or a reading circuit 13 varies depending on the location of the memory cell 11 selected. For that reason, when a select signal is to be transmitted to a group of memory cells 11 connected to the same word line WL, the timing of the memory cell 11 providing data (response speed) to a bit line pair (BL and /BL) varies between memory cells 11 of the group that are positioned far from the select circuit 12 (hereinafter referred to as distal side) and memory cells 11 of the group that are positioned near the select circuit 12 (hereinafter referred to as proximal side). A difference in response speed corresponds to a delay time due to parasitics (resistance and capacitance) or the word line WL. As a result, the reading speed between memory cells 11 varies.
Similarly, of a group of memory cells 11 connected to the same bit line pair (BL and /BL), the reading speed is varied due to bit line parasitics (resistance and capacitance) between distal side memory cells 11 and proximal side memory cells 11 with respect to a corresponding reading circuit 13. Accordingly, semiconductor memory device 10 is designed based on data propagation time of distal side memory cells 11 in order to avoid malfunction irrespective of whether the selected memory cell is a distal side memory cell 11 or a proximal side memory cell 11.
A more detailed description of problems of a conventional semiconductor memory device will now be given using a reading circuit in an SRAM as an example.
Referring now to FIG. 31, a circuit schematic diagram of a conventional memory cell block is set forth. The conventional memory cell block has n memory cells 11 that are connected to the same reading circuit 13 through a bit line pair (BL and /BL). The distance from reading circuit 13 is different for each memory cell 11. The parasitic resistance and parasitic capacitance of bit line pair (BL and /BL) causes the propagation time of data to vary from one memory cell 11 to another memory cell 11. The timing T of an activation signal for reading circuit 13 is set for a worst case memory cell 11 to provide an electrical potential difference xcex94V necessary at bit line pair (BL and /BL) for a normal operation of reading circuit 13. In this case, the worst case memory cell 11 can be the distal memory cell 11 with respect to reading circuit 13.
The delay of data signal transmission due to differences in distance from reading circuit 13 in a conventional memory cell block will now be described with reference to FIG. 32. FIG. 32(a) is a circuit schematic diagram of a conventional memory cell block illustrating current paths. FIG. 32(b) is a waveform diagram showing the electric potential waveform of bit lines when a proximal side memory cell is selected. FIG. 32(c) is a waveform diagram showing the electric potential waveform of bit lines when a distal side memory cell is selected.
As shown in FIG. 32(a), a proximal memory cell 111 with respect to reading circuit 13 sets the electric potential difference between bit line pair (BL and /BL) to xcex94V by taking a current path indicated by an arrow b. In proximal memory cell 111, as illustrated in FIG. 32(b), the electric potential xcex94V is reached at an early time because the electric resistance of bit line BL from memory cell 111 to reading circuit 13 is small.
On the other hand, as shown in FIG. 32(b), a distal memory cell 11n with respect to reading circuit 13 sets the electric potential difference between bit line pair (BL and /BL) to xcex94V by taking a current path indicated by an arrow c. In distal memory cell 11n, as illustrated in FIG. 32(c), the electric potential xcex94V is reached at a later time T because the electric resistance of bit line BL from memory cell 11n to reading circuit 13 is large. In this way, it can be seen that memory cell 11n needs more time to set an electric potential between bit line pair (BL and /BL) to xcex94V than proximal memory cell 111.
As shown in FIG. 32(c), reading circuit 13 is controlled with a timing T at which an electric potential difference xcex94V between a bit line pair (BL and /BL) is achieved for a read from distal memory cell 11n. Timing T is set to accommodate a worst-case scenario. Therefore, as illustrated in FIG. 32(b), when proximal memory cell 111 is selected, the electric potential difference between bit line pair (BL and /BL) at time T (when reading circuit 13 is activated) is xcex94V+xcex1. In other words, setting timing T to accommodate distal memory cell 11n is not optimal for proximal memory cell 111 which reaches an electric potential difference xcex94V earlier than timing T.
FIG. 33 illustrates a conventional approach for dividing a bit line. FIG. 33(a) is a circuit schematic diagram of a conventional memory cell block having 2n memory cells. FIG. 33(b) is a circuit schematic diagram of a conventional memory cell block obtained by dividing the number of memory cells connected to a bit line pair (BL and /BL) in two as compared to the conventional memory cell block of FIG. 33(a).
In FIG. 33(a), 2n memory cells (111 to 112n) are connected to bit line pair (BL and /BL). In FIG. 33(b), each bit line pair (of FIG. 33(a)) is divided so that only n memory cells of the 2n memory cells are connected to each divided bit line pair (BL and /BL) so that time to propagate data to reading circuit 13 from a distal memory cell 11n becomes closer to the time to propagate data to reading circuit 13 from a proximal memory cell 111.
In the example illustrated in FIG. 33(b), each bit line is divided to make the distal memory cell 11n closer to the proximal memory cell 111 to reduce the difference in data propagation time to reading circuit 13. However, the number of reading circuits 13 required has to be increased in accordance with the division multiple of the bit line (in this case, the number of reading circuits 13 must double). The increase in the number of reading circuits 13 results in the increase in chip size and thus, increases manufacturing costs.
Another technique for improving the reading speed is disclosed in JP 10-289585 A. FIG. 34 is a circuit schematic diagram of a conventional semiconductor memory device disclosed in JP 10-289585 A. Referring now to FIG. 34, a control circuit 15 assesses the position of a memory cell 11 to be selected based on address signals (ARn and ARn-1) and generates a select control signal based on the assessment. In response to the select control signal generated in control circuit 15, a select circuit 16 selects one of a plurality of voltages (Vref0 to Vref3) of different voltage levels and supplies the selected voltage to a memory cell array 17.
In the conventional semiconductor memory device of FIG. 34, the reading speed can be improved by setting different drive voltages in accordance with whether a proximal side memory cell 11 is selected or a distal side memory cell 11 is selected. However, the conventional semiconductor memory device of FIG. 34 needs additional circuits. Namely, control circuit 15 for assessing the position of a selected memory cell 11 and a voltage control circuit (not shown in FIG. 34) for generating different a plurality of voltages (Vref0 to Vref3) having different voltage levels. The additional circuits increase chip size and therefore can increase manufacturing costs.
As described above, conventional semiconductor memory devices of FIGS. 33 and 34 may achieve a reduction in differences in reading speeds between memory cells due to a difference in distance between memory cells a reading circuit. However, using the conventional approaches of FIGS. 33 and 34, the chip size may increase and therefore manufacturing costs may increase.
In view of the above discussion, it would be desirable to provide semiconductor memory device that may reduce the difference in reading speeds between distal side memory cells and proximal side memory cells while reducing an increase in chip size.
According to the present embodiments, a semiconductor memory device is disclosed. A semiconductor memory device may include a select circuit region, a reading circuit region, and a memory cell array region. A memory cell array region may include proximal memory cells and distal memory cells with respect to a select circuit region or a reading circuit region. Distal memory cells have a current drive characteristic that may be greater than a current drive characteristic of proximal memory cells. In this way, compensation may be provided and a data propagation delay difference due to parasitic values may be decreased.
According to one aspect of the embodiments, a semiconductor memory device may include a plurality of word lines disposed in a row direction and a plurality of bit lines disposed in a column direction. A plurality of memory cells may be placed at intersections of the plurality of word lines and the plurality of bit lines. Each memory cell may be connected to one of the plurality of word lines and one of the plurality of bit lines. Select circuits may be coupled to the word lines to select memory cells. Reading circuits may be connected to the bit lines to read data from the selected memory cells. Of a group of memory cells connected to a same one of the plurality of word lines, the current drive performance of distal side memory cells positioned far from the select circuits may be set higher than the current drive performance of proximal side memory cells positioned near the select circuits.
According to another aspect of the embodiments, a semiconductor memory device may include a plurality of word lines disposed in a row direction and a plurality of bit lines disposed in a column direction. A plurality of memory cells may be placed at intersections of the plurality of word lines and the plurality of bit lines. Each memory cell may be connected to one of the plurality of word lined and one of the plurality of bit lines. Select circuits may be coupled to the word lines to select memory cells. Reading circuits may be connected to the bit lines to read data from the selected memory cells. Of a group of memory cells connected to a same one of the plurality of bit lines, the current drive performance of distal side memory cells positioned far from the reading circuits may be set higher than the current drive performance of proximal side memory cells positioned near the reading circuits.
According to another aspect of the embodiments, each distal side memory cell may include insulated gate field effect transistors (IGFETs) that may have a larger gate width than corresponding IGFETs in the proximal side memory cells.
According to another aspect of the embodiments, each distal side memory cell may include IGFETs that may have a shorter gate length than corresponding IGFETs in the proximal side memory cells.
According to another aspect of the embodiments, each distal side memory cell may include IGFETs that may have channel regions doped with an impurity at a different impurity concentration than corresponding IGFETs in the proximal side memory cells.
According to another aspect of the embodiments, the impurity may include boron and the impurity concentration may be lower in the IGFETs in the distal side memory cells than in the corresponding IGFETs in the proximal side memory cells.
According to another aspect of the embodiments, the impurity may include phosphorus and the impurity concentration may be higher in the IGFETs in the distal side memory cells than in the corresponding IGFETs in the proximal side memory cells.
According to another aspect of the embodiments, the plurality of memory cells may be included in a memory cell array region. A connection adjusting region may be provided between the memory cell array region and the select circuits. The connection adjusting region may connect wires included in each select circuit with wires included in the memory cell array region after adjusting the positions of the wire in accordance with a pitch of the memory cells.
According to another aspect of the embodiments, the plurality of memory cells may be included in a memory cell array region. A connection adjusting region may be provided between the memory cell array region and the reading circuits. The connection adjusting region may connect wires included in each reading circuit with wires included in the memory cell array region after adjusting the positions of the wire in accordance with a pitch of the memory cells.
According to another aspect of the embodiments, a semiconductor memory device may include an output circuit coupled to receive data from a plurality of memory cell array regions. The plurality of memory cell array regions may include a proximal memory cell array region and a distal memory cell array region with respect to the output circuit. The proximal memory cell array region may include a plurality of proximal memory cells and the distal memory cell array region may include a plurality of distal memory cells. The current drive performance of the distal memory cells may be set higher than the current drive performance of proximal memory cells.
According to another aspect of the embodiments, each of the plurality of distal memory cells may have a pitch in a bit line direction larger than the pitch in a bit line direction of each of the plurality of proximal memory cells.
According to another aspect of the embodiments, each of the plurality of distal memory cells may have a pitch in a word line direction larger than the pitch in a word line direction of each of the plurality of proximal memory cells.
According to another aspect of the embodiments, each distal memory cell may include IGFETs that may have a larger gate width than corresponding IGFETs in the proximal memory cells.
According to another aspect of the embodiments, the semiconductor memory device may be a static random access memory (SRAM).
According to another aspect of the embodiments, each distal memory cell may include IGFETs that may have channel regions doped with an impurity at a different impurity concentration than corresponding IGFETs in the proximal memory cells.